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| Features * * * * * * Industry Standard Architecture Low Cost Easy-to-Use Software Tools High Speed Electrically Erasable Programmable Logic Devices 5 ns Maximum Pin-to-Pin Delay CMOS and TTL Compatible Inputs and Outputs Latch Feature Holds Inputs to Previous Logic States Advanced Flash Technology Reprogrammable 100% Tested High Reliability CMOS Process 20 Year Data Retention 100 Erase/Write Cycles 2,000V ESD Protection 200 mA Latchup Immunity Dual-in-Line and Surface Mount Packages in Standard Pinouts High Performance E2 PLD ATF22V10C Logic Diagram Pin Configurations Pin Name CLK IN I/O * VCC PD Function Clock Logic Inputs Bidirectional Buffers No Internal Connection +5V Supply Power Down CLK/IN IN IN IN/PD IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN TSSOP Top View ATF22V10C DIP/SOIC PLCC Top view Note: For PLCC, pins 1, 8, 15 and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and ground to 8, 15, 22. Rev. 0735C/22V10C-D-04/98 Description The ATF22V10C is a high performance CMOS (Electrically Erasable) Programmable Logic Device (PLD) which utilizes Atmel's proven electrically erasable Flash memory technology. Speeds down to 5 ns and power dissipation as low as 100 A are offered. All speed ranges are specified over the full 5V 10% range for industrial temperature ranges, and 5V 5% for commercial temperature ranges. Several low power options allow selection of the best solution for various types of power-limited applications. Each of these options significantly reduces total system power and enhances system reliability. Absolute Maximum Ratings* Temperature Under Bias................... -40C to +85C Storage Temperature...................... -65C to +150C Voltage on Any Pin with Respect to Ground........................ -2.0V to +7.0V (1) Voltage on Input Pins with Respect to Ground During Programming................... -2.0V to +14.0V (1) Programming Voltage with Respect to Ground...................... -2.0V to +14.0V (1) *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V dc, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V dc, which may overshoot to 7.0V for pulses of less than 20 ns. DC and AC Operating Conditions Commercial Operating Temperature (Case) VCC Power Supply 0C - 70C 5V 5% Industrial -40C - 85C 5V 10% 2 ATF22V10C ATF22V10C DC Characteristics Symbol IIL IIH ICC Parameter Input or I/O Low Leakage Current Input or I/O High Leakage Current Condition 0 VIN VIL(MAX) 3.5 VIN VCC C-5, 7, 10 C-10 C-5, 7, 10 C-10 C-5, 7, 10 C-10 Com. Ind. Com. Ind. Com. Ind. Com. Ind. 10 10 85 90 1 1 150 160 100 100 -130 -0.5 2.0 VIN = VIH or VIL, IOL = 16 mA VCC = MIN IOL = 12 mA VIN = VIH or VIL, IOH = -4.0 mA VCC = MIN Com., Ind. Mil. 2.4 0.8 VCC+0.75 0.5 0.5 Min Typ -35 Max -10 10 130 140 Units A A mA mA mA/MHz(2) mA/MHz(2) mA mA A A mA V V V V V V = MAX, Power Supply Current, CC VIN = MAX, Standby Outputs Open Clocked Power Supply VCC = MAX, Current Outputs Open V = MAX, Clocked Power Supply CC Outputs Open, Current f = 15 MHz Power Supply Current, VCC = MAX PD Mode VIN = 0, MAX Output Short Circuit VOUT = 0.5V Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage ICC2 ICC3 IPD IOS(1) VIL VIH VOL VOH Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. Low frequency only. See Supply Current versus Input Frequency curves. 3 AC Waveforms (1) Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. AC Characteristics (1) -5 Symbol Parameter tPD tCO tCF tS tH FMAX tP tW tEA tER tAP tAW tAR tSP tSPR Input or Feedback to Combinatorial Output Clock to Output Clock to Feedback Input or Feedback Setup Time Hold Time External Feedback 1/(tS + tCO) Internal Feedback 1/(tS + tCF) No Feedback Clock Period Clock Width Input or I/O to Output Enable Input or I/O to Output Disable Input or I/O to Asynchronous Reset of Register Asynchronous Reset Width Asynchronous Reset Recovery Time Setup Time, Synchronous Preset Synchronous Preset to Clock Recovery Time 6 3 2 2 3 5.5 4 4 4 6 5 7 3 0 142 166 166 6 3 3 3 3 7 5 4.5 5 7.5 7.5 10 Min 1 1 Max 5 4 3 3.5 0 125 (3) 142 166 8 3 3 3 3 8 6 6 8 10 9 12 Min 3 2 -7 Max 7.5 4.5 (2) -10 Min 3 2 4.5 0 90 117 125 Max 10 6.5 4 Units ns ns ns ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns 3.5 Notes: 1. See ordering information for valid part numbers. 2. 5.5 ns for DIP package devices. 3. 111 MHz for DIP package devices. 4 ATF22V10C ATF22V10C Power Down AC Characteristics (1, 2, 3) -5 Symbol Parameter tIVDH Valid Input Before PD High tGVDH Valid OE Before PD High tCVDH Valid Clock Before PD High tDHIX Input Don't Care After PD High tDHGX OE Don't Care After PD High tDHCX Clock Don't Care After PD High tDLIV tDLGV tDLCV tDLOV PD Low to Valid Input PD Low to Valid OE PD Low to Valid Clock PD Low to Valid Output Min Max Min -7 Max Min -10 Max Units ns ns ns 5 0 0 5 5 5 5 15 15 20 7.5 0 0 7 7 7 7.5 20 20 25 10 0 0 10 10 10 10 25 25 30 ns ns ns ns ns ns ns Notes: 1. Output data is latched and held. 2. HI-Z outputs remain HI-Z. 3. Clock and input transitions are ignored. Input Test Waveforms and Measurement Levels Output Test Loads: Commercial tR, tF < 3 ns Pin Capacitance (f = 1 MHz, T = 25C) (1) Typ CIN COUT Note: Max 8 8 Units pF pF Conditions VIN = 0V VOUT = 0V 5 6 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Power Up Reset The registers in the ATF22V10Cs are designed to reset during power up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, and starts below 0.7V, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3. The clock must remain stable during tPR. 5 V RST Parameter Description t PR Typ 600 Max 1,000 Units ns POWER tPR tS tW Power-Up Reset Time Power-Up Reset Voltage REGISTERED OUTPUTS VRST 3.8 4.5 V CLOCK Preload of Registered Outputs The ATF22V10C's registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF22V10C fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. Electronic Signature Word There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data. Programming/Erasing Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware & Software Support for information on software/programming. Input and I/O Pin Keeper Circuits The ATF16V8C contains internal input and I/O pin keeper circuits. These circuits allow each ATF16V8C pin to hold its previous value even when it is not being driven by an external source or by the device's output buffer. This helps insure that all logic array inputs are at known, valid logic levels. This reduces system power by preventing pins from floating to indeterminate levels. By using pin keeper circuits rather than pull-up resistors, there is no DC current required to hold the pins in either logic state (high or low). These pin keeper circuits are implemented as weak feedback inverters, as shown in the Input Diagram below. These keeper circuits can easily be overdriven by standard TTL- or CMOS-compatible drivers. The typical overdrive current required is 40 A. Input Diagram I/O Diagram 6 ATF22V10C ATF22V10C Functional Logic Diagram ATF22V10C 7 Ordering Information tPD (ns) 5 7.5 tS (ns) 3 3.5 tCO (ns) 4 4.5 Ordering Code ATF22V10C-5JC ATF22V10C-7JC ATF22V10C-7PC ATF22V10C-7SC ATF22V10C-7XC ATF22V10C-10JC ATF22V10C-10PC ATF22V10C-10SC ATF22V10C-10XC ATF22V10C-10JI ATF22V10C-10PI ATF22V10C-10SI ATF22V10C-10XI Package 28J 28J 24P3 24S 24X 28J 24P3 24S 24X 28J 24P3 24S 24X Operation Range Commercial (0C to 70C) Commercial (0C to 70C) 10 4.5 6.5 Commercial (0C to 70C) Industrial (-40C to 85C) Package Type 28J 24P3 24S 24X 28-Lead, Plastic J-Leaded Chip Carrier (PLCC) 24-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP) 8 ATF22V10C |
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